A window-type ball grid array (WBGA) semiconductor package is characterized in the use of a substrate formed with at least an opening (so-called “window”) penetrating through the same, wherein a chip is mounted on a surface of the substrate and covers the opening, a plurality of bonding wires are formed for electrically connecting the chip to the substrate via the opening of the substrate, and a plurality of solder balls are implanted on an opposing surface of the substrate for electrically connecting the chip to an external device. This package structure is suitably used for accommodating central-pad chips and yields significant benefits in terms of reducing wire length and structural profile of the semiconductor package.
A conventional WBGA semiconductor package, as shown in FIG. 6A, uses a substrate 10 having an upper surface 100 and a lower surface 101 and formed with an opening 102 penetrating through the substrate 10. A chip 11 is mounted on the upper surface 100 of the substrate 10 and covers the opening 102 in a face-down manner that bond pads 111 formed on an active surface 110 of the chip 11 are exposed via the opening 102. A plurality of bonding wires 12 are bonded to the bond pads 111 of the chip 11 and to the lower surface 101 of the substrate 10 via the opening 102 for electrically connecting the chip 11 to the substrate 10. Then, a lower encapsulant 13 is formed on the lower surface 101 of the substrate 10 for filling into the opening 102 and encapsulating the bonding wires 12, and an upper encapsulant 14 is formed on the upper surface 100 of the substrate 10 for encapsulating the chip 11. Finally, a plurality of solder balls 15 are implanted on the lower surface 101 of the substrate 10 at area free of the lower encapsulant 13, and act as input/output (I/O) connections for electrically connecting the chip 11 to an external device such as printed circuit board (PCB, not shown). Related prior arts include U.S. Pat. Nos. 5,920,118, 6,144,102, 6,190,943 and 6,218,731, wherein U.S. Pat. No. 5,920,118 uses a ceramic substrate as a chip carrier, and U.S. Pat. Nos. 6,144,102, 6,190,943 and 6,218,731 adopt a substrate made of an organic material such as BT (bismaleimide triazine) resin for accommodating chips; however, the ceramic or organic substrate is quite expensive in fabrication, making production costs of the semiconductor package undesirably increased.
Taiwan Patent Publication No. 411537 discloses a WBGA semiconductor package using a lead frame as a chip carrier, wherein the lead frame is composed of a plurality of leads, and a chip is mounted on a surface of the leads. Solder mask is applied over an opposing surface of the leads and formed with a plurality of openings for exposing predetermined ball-implanting portions on the leads where solder balls are bonded. However, this package structure causes significant drawbacks; one is that the process for applying solder mask over the leads is complex and cost-ineffective to perform, and gaps between adjacent leads are hardly filled by solder mask. Moreover, solder mask has relatively high moisture absorbability, which makes moisture easily accumulate in solder mask applied on the leads and leads to delamination at interface between solder mask and the leads.
Furthermore, the above semiconductor package in the use of a substrate or lead frame would be easily subject to a resin flash problem. For example of the package structure shown in FIG. 6A, when a molding process is performed for forming the upper encapsulant 14 and the lower encapsulant 13 on the substrate 10, as shown in FIG. 6B, the substrate 10 mounted with the chip 11 and bonding wires 12 is placed in an encapsulation mold 16 having an upper mold 17 and a lower mold 18, allowing the substrate 10 to be clamped between the upper and lower molds 17, 18. The upper mold 17 is formed with an upwardly recessed cavity 170 for accommodating the chip 11, and the lower mold 18 is formed with a downwardly recessed cavity 180 corresponding in position to the opening 102 of the substrate 10 for receiving the bonding wires 12 within the downwardly recessed cavity 180. When a resin material such as epoxy resin is injected into the encapsulation mold 16, it would fills into the upwardly recessed cavity 170 and the downwardly recessed cavity 180 to form the upper and lower encapsulants 14, 13 that respectively encapsulate the chip 11 and the bonding wires 12. However, due to a larger area on the substrate 10 being covered by the upwardly recessed cavity 170 than by the downwardly recessed cavity 180, a portion NC of the lower surface 101 of the substrate 10 adjacent to the lower encapsulant 13 can not be firmly clamped by the upper mold 17 or lacks clamping force from the upper mold 17, such that the resin material would easily flash to the portion NC of the lower surface 101 of the substrate 10 and contaminate predetermined ball-implanting portions formed on the lower surface 101 of the substrate 10 (as indicated by arrows in FIG. 6C). This flash contamination makes solder balls 15 not completely or securely bonded to the contaminated ball-implanting portions of the substrate 10, and thus degrades quality of electrical connection for fabricated package products.
Therefore, the problem to be solved herein is to provide a WBGA semiconductor package that can eliminate the above drawbacks in order to reduce fabrication costs and prevent delamination and resin flash from occurrence.